
| Course Code | : MAT429 |
| Course Type | : Area Elective |
| Couse Group | : First Cycle (Bachelor's Degree) |
| Education Language | : Turkish |
| Work Placement | : N/A |
| Theory | : 3 |
| Prt. | : 0 |
| Credit | : 3 |
| Lab | : 0 |
| ECTS | : 6 |
1-Teaching the basic information necessary for the operation of digital computers 2-Being able to design digital circuits
Digital systems, analog and digital systems, number systems, complements of numbers, number systems, complement finding algorithms, subtraction operation using complements, code systems, binary codes, numerical codes, alphanumeric codes, weighted codes, self-complementing codes, cyclic codes, gray codes, error detecting codes, error correcting code systems, Hamming codes, 2-error detecting and 1-error correcting code, Boolean algebra, binary Boolean algebra, Boolean expressions, standard forms, sum of standard products, product of standard sums, minterm, maxterm, two-variable Boolean operations, smallest competent operation sets, smallest expression, non-repetitive expression, simplification by map method, Karnaugh maps, three-four-five variable map, combinational circuit, sequential circuit, positive and negative logic, gates, propagation delay, fan-out value, analysis with basic gates, circuit design with basic gates, NAND and NOR gates, half adder, full adder, half subtractor, full subtractor, two’s complement calculating circuit
| Lec. Rıfat AŞLIYAN |
| 1. | Being able to learn numerical systems |
| 2. | Being able to convert between various number systems |
| 3. | Being able to convert between various number systems Being able to learn how code systems work |
| 4. | Being able to understand Hamming codes and how erroneous codes are corrected |
| 5. | Being able to grasp how Boolean algebra and simplification with Karnaugh maps work |
| 6. | Being able to learn basic information about circuits |
| 7. | Being able to design circuits |
| 1. | Mano, M., Kime, C.R., Logic and Computer Design Fundamentals, Prentice Hall, 2001 |
| 2. | Prof. Dr. Ünal Yarımağan, Sayısal Devrelerde Mantıksal Tasarım (Designing Logical Circuits) |
| Type of Assessment | Count | Percent |
|---|---|---|
| Midterm Examination | 1 | %40 |
| Final Examination | 1 | %60 |
| Activities | Count | Preparation | Time | Total Work Load (hours) |
|---|---|---|---|---|
| Lecture - Theory | 14 | 0 | 3 | 42 |
| Individual Work | 14 | 0 | 3 | 42 |
| Midterm Examination | 1 | 30 | 2 | 32 |
| Final Examination | 1 | 32 | 2 | 34 |
| TOTAL WORKLOAD (hours) | 150 | |||
PÇ-1 | PÇ-2 | PÇ-3 | PÇ-4 | PÇ-5 | PÇ-6 | PÇ-7 | PÇ-8 | PÇ-9 | PÇ-10 | PÇ-11 | PÇ-12 | PÇ-13 | PÇ-14 | PÇ-15 | PÇ-16 | PÇ-17 | PÇ-18 | |
OÇ-1 | 4 | 3 | 4 | |||||||||||||||
OÇ-2 | 4 | 3 | 4 | |||||||||||||||
OÇ-3 | 4 | 3 | 4 | |||||||||||||||
OÇ-4 | 4 | 3 | 4 | |||||||||||||||
OÇ-5 | 4 | 3 | 4 | |||||||||||||||
OÇ-6 | 4 | 3 | 4 | |||||||||||||||
OÇ-7 | 4 | 3 | 4 | |||||||||||||||